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MZ3500

4 9. VSYNC

[Circuit description]

When more than two UPD7220 GDC's are to l>e operated in

parallel, one must be assigned to the master and the other

to the slave in order to mantain synchronous display

timing. The master and the slave are determined according

to the table below. The above circuit shoud be used to

compare with the table description.

'^^'---^..^GpC-1 (character)

CH48 = 0 40 digit

CH48 = 1 80 digit

GDC-2 igraphic)''''''''''--.,.^^^

Without VRAM PWB

GDCl (character)

is the master.

GDC 1

8-bit structure (0816=0)

(48KB, 200 raster)

GDC 1

16-bit structure (0816=1)

(48 96KB, 400 rasters)

GDC 1 GDC2 (Graphic)

The master GDC must be set as irtdicated above.

[Oprational example]

If It was set to 80 digit, 16 bit/word mode SRES will be

0 when CH48 = 1, 0816 = 1 when not in the reset condi

tion. These signals are supplied to terminal A (weight 1),

B (weight 2), and G (gate), and set terminal Y3 of the

decoder 1C LS139 to "0", so that the YSYNC output of

the GDC2 is input to terminal EX SYNC of the GDC2.

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Sharp MZ-3500 Bedienungsanleitung Seite 41